CC=tile-cc

# PUT YOUR OWN INFO HERE
ATHENA=jeev
PROJ_PATH=/home/$(ATHENA)/vlsi6846

# INPUT PARAMETERS
INPUT=final.txt
C=1024
TIMELIMIT=180

vlsi: vlsi.o parser.o
	tile-cc -o vlsi vlsi.o parser.o -lm -lilib

run: vlsi
	/opt/bin/tm-wrapper --pci --upload $(PROJ_PATH)/vlsi vlsi --upload $(PROJ_PATH)/inputs/$(INPUT) $(INPUT) --run - vlsi $(INPUT) -C $(C) -timelimit $(TIMELIMIT) -

clean:
	rm -f vlsi vlsi.o parser.o *~ $(ATHENA).* vlsi_local

vlsi-local:
	gcc vlsi_local.c parser.c -o vlsi_local -lm

run-local: vlsi-local
	./vlsi_local $(PROJ_PATH)/inputs/$(INPUT) -C $(C) -timelimit $(TIMELIMIT)
